View P9030-0NTGI8_8005633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

single chip wireless power transmitter ic for tx - a1 product datasheet idtp9030 revi sion 1.0. 2 1 ? 2012 integrated device technology, inc . features ? single - chip 5w solution for wireless power consortium (wpc) - compliant power transmitter design a1 ? conforms t o wpc specification version 1.1 specifications ? 191 v operating input voltage ? integrated half - bridge inverter ? closed - loop power transfer con trol between base station and mobile device ? demodulates and decodes wpc - compliant message packets ? 5v regulated dc/dc converter ? integrated reset function ? proprietary back C channel communication ? i 2 c interface ? open - drain led indicator outputs ? over - temperature /voltage/current protection ? s ecurity and encryption up to 64 bits ? foreign object detection (fod) for safety applications ? wpc - compliant wireless charging base stations package: 6x6 - 48 tqfn (see page 27 ) or dering information (see page 28 ) descrip tion the idtp9030 is a highly - integrated single - chip wpc - compliant wireless power transmitter ic for power transmitter design a1. the device operates with a 19v (1v) adapter , and supplies an integrated half - bridge in verter for dc/ac conversion. it contr ols the transferred power by modulating the switching frequency of the half - bridge inverter from 110khz to 205khz at a fixed 50% duty cycle specified by the wpc specification for an a1 transmitter. it contains logic circuits required to demodulate and d ecode wpc - compliant message packets sent by the mobile device to adjust the transferred power. the idtp9030 is an intelligent device that periodically pings the area surrounding the base station to detect a mobile device for charging while minimizing idle power. once the mobile device is detected and authenticated, the idtp9030 continuously monitors all communications from the mobile device, and adjusts the transmitted power accordingly by varying the switching frequency of the half - bridge inverter. the id tp9030 fea tures a proprietary back - channel communication mode which enables the device to communicate to idts wirele ss power receiver solutions (e.g. idtp9020). this feature enables additional layers of capabilities relative to standard wpc requirements. this device also features optional security and encryptions to securely authenticate the receiver before transferring power. this feature is available when an idtp9020 is u s ed for the receiver. the device includes over - temperature/voltage/current protect ion and a foreign object detection (fod) method to protect the base station and mobile device from overheating in the presence of a metallic foreign object. it manages fault conditions associated with power transfer and controls status leds to indicate op erating modes. typical application circuit mobile device receiver output load control system power pick - up comm cont mod sensing control out pwr base station transmitter(s) input power control system power generation comm cont demod in pwr sensing control induction load reflection comm control wireless interface
idtp9030 product datasheet revision 1.0. 2 2 ? 2012 integrated device technology, inc. figure 1 . idtp9030 simplified application schematic note 1: npo/c0g - type ceramic capacitor. note 2: for pcb layout, use single - point reference (st ar ground), refer to design schematic in figure 15 ). note 3: in circuit at gpio_2, r top is required to linearize the temperature range of the thermistor, r ntc . please contact idt fo r a spreadsheet calculator to guide thermistor selection. 8 8 u f w p c t x - a 1 i d t p 9 0 3 0 ` s c l s d a r e g _ i n r e s e t r e s e t s d a s w p g n d v o s n s i s n s h p f b u z z e r l x b s t l d o 2 p 5 v _ i n b u c k 5 v t b u c k 5 v t _ i n 1 0 u f 1 u f g n d 2 g p i o _ 1 l d o 5 v l d o 5 v l d o 2 p 5 v b u c k 5 v t _ s n s 3 . 3 n f 1 1 . 8 n f 1 1 u f 1 u f / 2 5 v l d o 2 p 5 v 4 . 7 u h 4 7 n f 1 0 u f b u c k 5 v t 1 . 5 k 1 0 k 2 2 n f 2 0 k 2 0 k 4 7 k 4 . 7 n f 1 1 0 k 1 u f s c l 4 7 k 5 . 1 k l e d b r t o p 5 . 1 k l e d a g p i o _ 0 g p i o _ 2 3 g p i o _ 3 g p i o _ 4 i n a d a p t o r 4 7 k r n t c 2 . 2 n f 1 0 0 n f 1 2 5 0 v 1 . 2 n f 1 v o 1 u f r e f g n d a g n d d g n d e p ( 3 x 3 3 n f ) ( 4 x 2 2 u f ) en en
revision 1.0. 2 3 ? 2012 integrated device technology, inc. idtp9030 product datasheet absolute maxi mum ratings these absolute maximum ratings are stress ratings only. stresses greater than those listed below ( table 1 and table 2 ) may cause permanent damage to the device. functional operation of the idtp9030 at absolute maximum ratings is not implied. ex posure to absolute maximum rating conditions for extended periods may affect long - term reliability. table 1 . ab solute maximum ratings summary. a ll vo ltages are referr ed to ground , unless otherwise noted . pin s maximum ra ting units buck5vt_in, in, reg_in. these pins must be connected together at all times. - 0.3 to 24 v , lx, sw 5 - 0.3 to 24 v bst 5 - 0.3 to 29 v ldo2p5v, xtal/clk_in, xtal/clk_out - 0.3 to 2.75 v agnd, dgnd, pgnd, refgnd - 0.3 to +0.3 v buck5vt_sns, buck5vt, gpio _0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, hpf, isns, ldo2p5v_in, ldo5v, reset, scl, sda, vosns - 0.3 to +5.5 v table 2 . package thermal information symbol description maximum rating units ? ja thermal resistance junction to ambient (ntg48 - tqfn) 30.8 ? c/w ? jc thermal resistance junction to case (ntg48 - tqfn) 14.6 ? c/w ? jb thermal resistance junction to board (ntg48 - tqfn) 0.75 ? c/w t j junction temperature - 40 to +150 ? c t a ambient op erating temperature - 40 to +85 ? c t stg storage temperature - 55 to +150 ? c t lead lead temperature (soldering, 10s) +300 ? c note 1: the maximum power dissipation is p d(max) = (t j(max) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable pow er dissipation will result in excessive die temperature, and the device will enter thermal shutdown. note 2: this thermal rating was calculated on jedec 51 standard 4 - layer board with dimensions 3 x 4.5 in still air conditions. note 3: actual thermal res istance is affected by pcb size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. note 4: for the ntg48 package, connecting the 4.1 mm x 4.1 mm ep to internal/external ground planes with a 5x5 matrix of pcb plated - through - hole (pth) vias, from top to bottom sides of the pcb, is recommended for improving the overall thermal performance. note 5 : if the voltage at vin is less than 24v, limit the voltages on , lx, sw to v(vin)+0.3v and the voltage on bst to v(vin)+5v.
idtp9030 product datasheet revision 1.0. 2 4 ? 2012 integrated device technology, inc. table 3 . esd information test model pins maximum ratings units hbm all, except in 1000 v only in (37, 38 and 39) 800 cdm all 500 v
revision 1.0. 2 5 ? 2012 integrated device technology, inc. idtp9030 product datasheet block diagram figure 2 . idtp9030 internal functional block diagram
idtp9030 product datasheet revision 1.0. 2 6 ? 2012 integrated device technology, inc. electrical character istics = reset = 0 v , in = reg_i n = buck5vt_in = 19v. t a = - 40 to +85 ? c, unless otherwise noted. typical values are at 25 ? c, unless otherwise noted. table 4 . device characteristics symbol description conditions min typ max units half - bridge inverter v in input s upply operating voltage range 1 18 20 v i in 2 i in_a standby input current after power - up sequence complete . n o coil, no load at sw, ldo5v, ldo2 p5v, lx . (no wireless power transfer to battery.) 8 15 ma i in_s sleep mode input current = 5v to v in 7 50 a f sw_low switching frequency at sw wpc operating range, in compliance with wpc requirements 110 khz f sw_high 205 khz r ds(on)_hs between in and sw 175 m r ds(on)_ls between sw and pgnd 130 m uvlo and inverter ocp v in_uvlo under - volta ge protection trip point v in rising 10.3 v v in falling 9.0 hysteresis 625 mv i in_ocp over - current protection trip point v in = 20v, cycle - by - cycle protection. 1.8 2.4 a dc - dc conv erter (for bias ing internal circuitry only ) 3 v buck5vt_in inpu t voltage range 1 18 20 v v buck5vt output voltage external i load = 25ma 4.5 5.5 v i out external load 4 80 ma f sw switching frequency at lx 3 mhz low drop out regulators (for bias ing internal circuitry only ) 3 ldo2p5v 3 v ldo2p5v_in input voltage range supplied from buck5vt 5 v v ldo2p5v output voltage i load = 2ma 2.5 v i out external load 5 ma ldo5v 3 v reg_in input voltage range see note 1. 18 20 v v ldo5v output voltage i load = 2ma 5 v
revision 1.0. 2 7 ? 2012 integrated device technology, inc. idtp9030 product datasheet electrical character istics = reset = 0v, in = reg_in = buck5vt_in = 19v. t a = - 40 to +85 ? c, unless otherwise noted. typical values are at 25 ? c, unless otherwise noted. table 5 . device characteristics , continued symbol description conditions min typ max units thermal shutdow n t sd thermal shutdown temperature rising threshold 140 ? c temperature falling threshold 110 v ih 900 mv v il 550 mv i en en input current v en = 5v 7.5 a v en = v i n = 20v 56 a general purpose inputs / outputs (gpio ) v ih input threshold high 3.5 v v il input threshold low 1.5 v i lkg input leakage - 1 +1 a v oh output logic high i oh = - 8ma 4 v v ol output logic low i ol =8ma 0.5 v i oh output curren t high - 8 ma i ol output current low 8 ma reset v ih input threshold high 3.5 v v il input threshold low 1.5 v i lkg input leakage - 1 +1 a scl, sda (i 2 c interface) f scl clock frequency eeprom loading, step 1, idtp9030 as master 100 k hz f scl clock frequency eeprom loading, step 2, idtp9030 as master 3 00 khz f scl clock frequency idtp9030 as slave 0 400 khz t hd;sta hold time (repeated) for start condition 0.6 s t hd; dat data hold time cbus - compatible masters 5 s i 2 c - bus devices 10 ns t low clock low period 1.3 s t high clock high period 0.6 s t su;sta set - up time for repeated start condition 100 ns
idtp9030 product datasheet revision 1.0. 2 8 ? 2012 integrated device technology, inc. electrical character istics = reset = 0v, in = reg_in = buck5vt_in = 19v. t a = - 40 to +85 ? c, unless otherwise noted. typical values are at 25 ? c, unless otherwise noted. table 6 . device characteristics , continued symbol description conditions min typ max units t buf bu s free time between stop and start condition 1.3 s c b capacitive load for each bus line 100 pf c bin scl, sda input capacitance 5 5 pf v il input threshold low w hen powered by device 5v 1. 5 v v ih input threshold high 3.5 v i lkg leakage current - 1.0 1.0 a v ol output logic low (sda) i p d = 2 ma (note 1) 0 .5 v i oh output current high - 2 ma i ol output current low 2 ma analog - to - digital converter n adc conversion resolution 12 bit f sample sampling rate 62.5 ksps channel number of channels at adc mux input 8 adc clk adc c lock frequency 1 mhz v in_fs full - scale input voltage 2.5 v microcontroller f clock clock frequency 40 mhz v in input voltage 2.5 v note 1: buck5vt_in, in, reg_in. these pins must be connected together at all times. note 2: this current is t he sum of the input currents for in, reg_in and buck5vt_in. note 3: dc - dc buck5vt, ldo2p5v and ldo5v are intended only as internal device supplies and must not be loaded externally except for the eeprom, thermistor, led, buzzer and pull up resistor loads ( up to an absolute maximum of 25 ma), as recommended in figure 15 wpc qi c ompliance schematic and table 6 wpc qi compliance bill of materials. note 4: any external load at the output of the dc/dc converter must not inject noise onto the output node, and care must be taken with parasitic inductance and capacitance. note 5: guaranteed by design.
revision 1.0. 2 9 ? 2012 integrated device technology, inc. idtp9030 product datasheet pin configuration figure 3 . idtp9030 pin configuration (ntg48 tqfn - 48l 6.0 mm x 6.0 mm x 0.75 mm, 0.4mm pit ch) n c n c n c n c n c g n d n c h p f i s n s i n i n i n 3 6 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 5 n c 1 g p i o _ 6 t q f n - 4 8 l 3 4 5 6 7 8 9 1 0 1 1 1 2 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 g p i o _ 5 g p i o _ 4 g p i o _ 3 g p i o _ 2 g p i o _ 1 g p i o _ 0 s c l s d a x t a l / c l k _ i n x t a l / c l k _ o u t r e s e t r e f g n d r e g _ i n l d o 5 v l d o 2 p 5 v l d o 2 p 5 v _ i n b u c k 5 v t b s t a g n d d g n d n c b u c k 5 v t _ i n s w s w s w p g n d n c p g n d p g n d p g n d v o s n s l x b u c k 5 v t _ s n s e n e p ( c e n t e r e x p o s e d p a d )
idtp9030 product datasheet revision 1.0. 2 10 ? 2012 integrated device technology, inc. pin description table 7 . idtp9030 ntg48 package pin functions by pin number () pin name type description 1 gpio_6 i/o general purpose input/output 6 2 gpio_5 i/o general purpose input/output 5 3 gpio_4 i/o general purpose in put/output 4 4 gpio_3 i/o general purpose input/output 3 5 gpio_2 i/o general purpose input/output 2 6 gpio_1 i/o general purpose input/output 1 7 gpio_0 i/o general purpose input/output 0 8 scl i/o i 2 c clock 9 sda i/o i 2 c data 10 xtal/clk_in i crys tal or clock input. if not used, must be connected to gnd. 11 xtal/clk_out o crystal or clock output. if not used, must be left unconnected. 12 reset i active - high chip reset pin. a 1f ceramic capacitor must be connected between this pin and ldo5v , and a 100k resistor to g d . 13 i active - low enable pin. device is suspended and placed in low current (sleep) mode when pulled high. tie to gnd for stand - alone operation. 14 refgnd - signal ground connection. must be connected to agnd. 15 reg_in 1 i a 1f ceramic capacitor must be connected between this pin and gnd. this pin must be connected to pins 37, 38, and 39. 16 ldo5v 2 o a 1f ceramic capacitor must be connected between this pin and gnd. 17 ldo2p5v 2 o 2.5v ldo output. a 1f ceramic capacito r must be connected between this pin and gnd. 18 ldo2p5v_in i 2.5v ldo input. the ldo2p5v_in input must be connected to buck5vt. a 1f ceramic capacitor must be connected between this pin and gnd. 19 buck5vt 2 i power and digital supply input to internal circuitry.
revision 1.0. 2 11 ? 2012 integrated device technology, inc. idtp9030 product datasheet table 7 . idtp9030 ntg48 package pin functions by pin number () pin name type description 20 bst i bootstrap pin for buck converter top switch gate drive supply. 21 agnd - analog ground connection. connect to signal ground. must be connected to refgnd. 22 dgnd - digital ground connection. must be connected to gnd. 23 nc nc not internally connected. 24 buck5vt_in 1 i buck converter power supply input. connect 0.1uf and 1f ceramic capacitors betw een this pin and pgnd. . this pin must be connected to pins 37, 38, and 39. 25 buck5vt_sns i buck regulator feedback. connect to the high side of the buck converter output capacitor . 26 lx o switch node of buck converter. connects to one of the inductor s terminals. 27 vosns i tx - a1 coil voltage sense input. 28 pgnd - power ground. 29 pgnd - power ground. 30 pgnd - power ground. 31 nc nc not internally connected. 32 pgnd - power ground. 33 sw o pins 33, 34, and 35 must be connected together. i nve rter switch node. must be connected to capacitor in series with tx - a1 coil. 34 sw o 35 sw o 36 nc nc not internally connected. 37 in 1 i inverter power supply input. connect at least four 22f x 25v ceramic capacitors and a 0.1f capacitor between this pin and ground, as close to the pin as possible. connect all three pins (37, 38, 39) in parallel. 38 in 1 i 39 in 1 i 40 isns o isns output signal
idtp9030 product datasheet revision 1.0. 2 12 ? 2012 integrated device technology, inc. table 7 . idtp9030 ntg48 package pin functions by pin number () pin name type description 41 hpf i high pass filter input 42 nc internal connection, must be connected to gnd. 43 gnd - ground 44 nc internal connection, must be connected to gnd. 45 nc internal connection, must be connected to gnd. 46 nc internal connection, must be connected to gnd. 47 nc internal connection, must be connected to gnd. 48 nc internal connection, do not connect. ep center exposed pad thermal ep is on the bottom of the package and must be electrically tied to gnd. for thermal performance, solder to a large copper pad embedded with a pattern of plated through - hole vias. the die is not electrically bonded to the ep, and the ep must not be used as current - carrying electrical connection. note 1: in, reg_in, buck5vt_in. t hese pins must be connected together at all times. note 2: dc - dc buck5vt , ldo2p5v , and ldo5v are intended only as internal device suppl ies and must not be loaded externally except for the eeprom, thermistor, led, buzzer and pull up resistor loads (up to an absolute maximum of 25 ma), as recommended in figure 15 wpc qi c ompliance schematic and table 6 wpc qi compliance bill of materials.
revision 1.0. 2 13 ? 2012 integrated device technology, inc. idtp9030 product datasheet typical performance characteristics , in = buck5vt_in = reg_in = 19v, ta = 25 o c. unless otherwise noted. figure 4 . efficiency vs. rx output power with idtp9020 receiver figure 5 . spacing between tx and rx coils is 2 mm 10.00% 20.00% 30.00% 40.00% 50.00% 60.00% 70.00% 80.00% 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency rx output power (w) system efficiency versus rx output power: tx input to rx output (idtp9030 "qi" tx - a1 evaluation kit and idtp9020 csp engineering sample pcb v1.0) 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 efficiency rx output power (w) efficiency versus rx output power: tx dc - to - ac (idtp9030 "qi" tx - a1 evaluation kit and avid technologies, inc., qi receiver simulator)
idtp9030 product datasheet revision 1.0 .2 14 ? 2012 integrated device technology, inc. systems applications diagram figure 6 . idtp9030/idtp9020 simplified systems application diagram l o a d p o w e r c d c s c r m m o d u l a t i o n m o d u l a t i o n c m l s c p l p + - i n v e r t e r 8 8 u f w p c t x - a 1 i d t p 9 0 3 0 ` s c l s d a r e g _ i n r e s e t r e s e t _ t s d a _ t s w p g n d v o s n s i s n s h p f b u z z e r l x b s t l d o 2 p 5 v _ i n b u c k 5 v t b u c k 5 v t _ i n 1 0 u f 1 u f g n d 2 g p i o _ 1 l d o 5 v l d o 5 v _ t l d o 2 p 5 v b u c k 5 v t _ s n s 3 . 3 n f 1 1 . 8 n f 1 1 u f 1 u f / 2 5 v l d o 2 p 5 v _ t 4 . 7 u h 4 7 n f 1 0 u f b u c k 5 v t 1 . 5 k 1 0 k 2 2 n f 2 0 k 2 0 k 4 7 k 4 . 7 n f 1 1 0 k 1 u f s c l _ t 4 7 k 5 . 1 k l e d b r t o p 5 . 1 k l e d a g p i o _ 0 g p i o _ 2 3 g p i o _ 3 g p i o _ 4 i n a d a p t o r 4 7 k r n t c 2 . 2 n f 1 0 0 n f 1 2 5 0 v 1 . 2 n f 1 v o 1 u f r e f g n d a g n d d g n d e p ( 3 x 3 3 n f ) ( 4 x 2 2 u f ) _ t 1 u f i d t p 9 0 2 0 r e c _ o u t 1 1 . 4 u h 1 8 3 n f 2 n f e n l d o 2 p 5 v _ i n 1 u f u s b / a d p _ i n r e c _ o u t s c l s d a r e s e t 2 2 n f g p i o _ 0 g p i o _ 1 g p i o _ 2 g p i o _ 3 g p i o _ 4 g p i o _ 5 g p i o _ 6 g p i o _ 6 g p i o _ 5 g p i o _ 4 g p i o _ 3 g p i o _ 2 g p i o _ 1 g p i o _ 0 i n _ p i n _ p r e g _ i n i n _ m i n _ m e n g n d l d o 2 p 5 v _ i n u s b _ i n b u c k 5 v r _ i n b u c k 5 v r _ i n s c l s d a a g n d d g n d r e s e t a c m _ p 2 2 n f a c m _ m 3 3 0 n f z r e f _ m 3 3 0 n f z r e f _ p r e f g n d 1 0 u f r e c _ o u t 4 0 u f 1 u f l d o 5 v 1 u f l d o 2 p 5 v 4 . 7 u f 1 0 u f b u c k 5 v r 4 7 n f 4 7 n f r e c _ o u t r e c _ o u t p g n d l x l x l d o 5 v l d o 2 p 5 v b u c k 5 v r _ s n s u s b _ o u t i s n s b s t r e c _ o u t l x b u c k 5 v r b u c k 5 v r i n _ p i n _ m b u c k 5 v r _ i n l d o 5 v l d o 5 v 1 0 k 1 0 0 1 0 0 k 2 . 7 k 2 . 7 k 1 0 0 n f 5 k 5 k 5 k 5 k 5 k 5 k en
revision 1.0 .2 15 ? 2012 integrated device technology, inc. idtp9030 product datasheet theory of operatio n the i dt p9030 is a highly - integrated wpc 1 (wireless power consortium) - compliant wireless power char ging ic solution for the transmitter b ase station. it can deliver more than 5w of power to the receiver when used with the idtp9020 or 5w in wpc qi mode using near - field magnetic induction as a m eans to transfer energy. it is the industrys first single - chip wpc - compliant solut ion designed to drive a wpc - compliant type - a1 transmitter coil. o verview figure 2 shows the block diagram of the idtp9030. when the vin_uvlo block detects that the voltage at in, reg_in, and buck5vt_in (all connected together externally) is above the vin _rising threshold and en is at a logic low, the enable sequence circuitry activates the voltage reference, the 5v and 2.5v ldo s , the 5v buck switching regulator, and the driver control for the output inverter . the voltages at the outputs of t he ldos and the buck regulator are monitored to ensure that they remain in regulation , and the adapter voltage, coil current, and internal temperature are monitored . the driver control block converts a pwm signal from the mcu to the gate drive signals r equired by the output inverter to drive the external re s o n ant tank. communication packets from the receiver in the mobile device are recovered by the demodulator and converted to digital signals that can be read by the mcu. several internal voltages an d the external thermistor voltage (through gpio2) are converted to their digital representations by the adc and supplied to the mcu. five gpio ports are available to the system designer for measuring an external temperature (ambient or inductor, for exampl e) and driving leds and a buzzer. the clock for the mcu and other circuitry is generated by either an external crystal or an internal rc oscillator. i 2 c sda and scl pins permit communication with an external device or host. note 1 - refer to the wpc speci fication at http://www.wirelesspowerconsortium.com/ for the most current information under voltage lockout (uvlo) the idtp9030 has a built - in uvlo circuit that monitors the input voltage and enables no rmal operation, as shown in figure 7 . figure 7 . v in versus uvlo threshold with /en low . over - current/voltage/temperature protection the current in the inverter is monitored by an analog current limit block. if the instantaneo us coil current exceeds 2a, the chip is shut down. vin_ovp mo nitors the voltage applied to the idtp9030 by the external ac adapter and shuts the part down if the adapter voltage rises above 24v, to protect against excessive power transfer to the receiver. the internal temperature is also monitored, and the part is temporarily deactivated if the temperature exceeds 140c and reactivated when the temperature falls below 1 1 0c. driver control block and inverter the driver control block contains the logic, s hoot - through protection, and gate drivers for the on - chip power fets. the fets are configured as a very large inverter that switches the sw pin between the voltage at in and ground at a rate set by the mcu . t i m e ( 1 s / d i v ) v c o i l ( 1 0 v / d i v ) u v l o e x i t e v e n t v i n ( 5 v / d i v ) v i n = 1 0 v 0 v 0 v
idtp9030 product datasheet revision 1.0 .2 16 ? 2012 integ rated device technology, inc. demodulator power is transferred from the tr ansmitter to the receiver through their respective coils: a loosely - coupled transformer. how much power is transferred is determined by the transmitters switching frequency (110khz - 205khz), and is controlled by the receiver through instructions sent back through the coils to the transmitter to change its frequency, end power transfer, or do something else. the instructions take the form of data packets, which are capacitively coupled into the idtp9030 s demodulator through the hpf pin. recovering the da ta packets is the function of the demodulator. understanding the packets is up to the mcu. output voltage sense the voltage at the junction of the external inductor and capacitor that comprise the resonant tank is monitored by the vosns block, digitized b y the adc, and fed to the digital control logic. the control algorithm also requires knowledge of the voltage across the inverter, so that voltage is also processed by the adc and sent to the digital block . micro - controller unit (mcu) the idtp9030s mcu p rocesses the algorith m, commands, and data that cont rol the p ower transferred to the reciever. the mcu is provided with ram and rom, and parametric trim and operational modes are set at the factory through the one - time programming (otp) block , read by the mcu at power - up . communication with external memory is performed through i 2 c via the scl and sda pins. applications information the recommended applications schematic diagram is shown in figure 1 5 . the idt p 9030 operates with a 19v dc (1v) input . the swi tchin g frequency varies from 110khz to 205khz. at the 205khz limit the duty cycle is also variable . the power transfer is controlled via change s in switching frequency. the b ase or tx - side has a series resonance circuit made of a wpc type - a1 coil (~ 24 ? h) and a s eries resonant capacitor (~ 100nf) circuit driven by a half - bridge inverter , as shown in figure 8. figure 8. half bridge inverter tx coil driver. figure 8 shows the resonant tank configuration from the wpc specificat ion. idt has found that the circuit of figure 9 is preferred for lower noise in the demodulation channel. figure 9. half bridge inverter tx coil driver. external chip reset and en the idtp9030 can be externally reset by pulling the reset pin to a logic high above the v ih level. th e reset pin is a dedicated high - impedance active - high digital input , and the effect is similar to the power - up reset function. because of the internal low voltage monitori ng scheme, the use of the external reset pin is not mandatory. a manual external reset scheme can be added by connecting 5v to the reset pin through a simple switch. when reset is high , the microcontrollers registers are set to the default configuration. when the reset pin is released to a low, the microcontroller starts executing the code from the boot address. if the application is in a noisy environment, an external rc filter is recommended (see figure 1 0 for reference) 1 9 v d r i v e r f s w a 1 c o i l 1 0 0 n f 2 4 ? h 1 9 v d r i v e r f s w 2 4 ? h a 1 c o i l 1 0 0 n f
revision 1.0 .2 17 ? 2012 integrated device technology, inc. idtp9030 p roduct datasheet figu re 1 0 . external pushbutton reset circuit . when the en pin is pulled high, the device is suspended and placed in low current (sleep) mode. if pulled low, the device is active . figure 11 . /en function . the curren t into en is about , or close to zero if v( en ) is less than 2v. xtal_clk/in and xtal_clk/out a 32.768khz crystal connected between the xtal/clk_in and xtal/clk_out pins establishes a precise time base. either tha t clock or the output of an on - chip rc oscillator is provided to the input of a pll to generate the system clock. idt recommends using the internal oscillator. system feedback control (wpc) the idt p 9030 contains logic to demodulate and decode error pack ets sent by the mobile device (rx - side) , and adjusts power transfer accordingly. the idt p 9030 varies the switching frequency of the half bridge inverter between 110khz to 205 khz. to adjust power transfer. the mobile device controls the amount of power tra nsfer red via a communication link that exists from the mobile device to the base station. the mobile device (idtp9020 or another wpc - compliant receiver) communicates with the idtp9030 via communication packets. each packet has the following format: table 5 C data packet format. preamble header message checksum the overall system behavior between the transmitter and receiver follows the state machine diagram below: figure 12 . system state machine diagram the idt p 9030 performs four phases: selection, ping, identification & configuration, and power transfer. start (selection) phase l d o 5 v r e s e t p u s h b u t t o n s w i t c h c 1 0 . 1 ? f c 2 1 ? f r 1 0 k ~ 1 0 0 k t i m e ( 1 m s / d i v ) b u c k 5 v o u t ( 2 . 5 v / d i v ) e n \ r i s i n g e d g e f u n c t i o n e n \ ( 5 v / d i v ) 0 v 0 v
idtp9030 product datasheet revision 1.0 .2 18 ? 2012 integ rated device technology, inc. in this phase, the idt p 9030 operates in a low power mode to determine if a potential receiver has been placed on the coil surface prior to the ping state. twice a second, the idt p9030 applies a brief ac signal to its coil and listens for a response. ping phase in this phase, the idt p 9030 applies a power signal at 175 khz with a fixed 50% duty cycle and attempts to establish a communicati on link with a m obile device. required pack et(s) in ping : 1. signal strength packet (0x01) the m obile device must send a signal strength packet within a time period specified by the wpc , otherwise the power signal is terminat ed and the process repeats. the m obile device calculates the signal s trengt h packet value, which is an unsigned integer value between 0 - 255, based on this formula: w here u is a monitored variable (i.e. rectified voltage/current/power) and u max is a maximum value of that monitored variable expected during the digital ping phase at 175 khz. if the idt p 9030 does not detect the start bit of the header byte of the signal strength p acket during the ping phase , it removes the power signal after a delay . if a signal strength packet is received, the idt p 9030 goes to the identification and configuration phase. if t he idt p 9030 does not move to the identification and configuration phase after receiving the signal strength packet, or if a packet othe r than a signal strength packet is received, then power is terminated . identification and configuration (id & config) in this phase, the idt p 9030 tries to identify the mobile device and collects configuration information. required packet(s) in id & config : 1. identification packet (0x71) 2. extended identification packet (0x81) * 3. configuration packet (0x51) * if ext bit of 0x71 p acket is set to 1. also, the idt p 9030 must correctly receive the following sequence of packets without changing the operating point (175 khz @ 50% duty cycle): 1. identification packet (0x71) 2. extented identification (0x81) 3. up to 7 optional configuration packe ts from the following set: a. power control hold - off packet (0x06) b. proprietary packet (0x18 C 0xf2) c. reserved packet 4. configuration packet (0x51) if the idt p 9030 does not detect the start bit of the header byte of the next packet in the sequence within a wpc - sp ecified time after receiving the stop bit of the checksum byte of the preceding signal strength packet, then the power signal is removed within after a delay . if a correct control packet in the above sequence is received late, or if control packets that ar e not in the sequence are received, the idt p 9030 removes the power signal after a delay. power transfer phase in this phase, the idt p 9030 adapts the power transfer to the receiver based on control data it receives in control error packets. required packet (s) in power transfer : 1. control error packet (0x03) 2. rectified power packet (0x04) for this purpose, the idt p 9030 may receive zero or more of the following packets: 1. control error packet (0x03) 2. rectified power packet (0x04) 3. charge status packet (0x05) 4. end pow er transfer packet (0x02) 5. any proprietary packet 6. any reserved packets if the idt p 9030 does not correctly receive the first control error packet in time , it removes the power signal after a delay . because control error packets come at a regular interval, th e idt p 9030 expects a new control error packet after receiving the stop bit of the checksum byte of the preceding control error packet. if that does not
revision 1.0 .2 19 ? 2012 integrated device technology, inc. idtp9030 p roduct datasheet happen, then the idt p 9030 removes the power signal. similary, the idt p 9030 must receive a rectified powe r packet within a wpc - specified time after receiving the stop bit of the checksum byte of the configuration packet (which was received earlier in the identification and configuration phase) . o therwise , it removes the power signal. upon receiving a control error value, the idt p 9030 makes adjustments to its operating point after a delay to enable the primary coi l current to stabilize again after communication. if the idt p 9030 correctly receives a packet that does not comply with the sequence, then it removes the power signal. foreign object detection (fod) in addition to over - temperature protection, the idt p 9030 employs a proprietary fod technique for safety which detects foreign objects placed on the base station. the fod algorithm is multi - layered and issue s warnings depending on the severity of the warning. the fod warning comes on during the ping phase indicating the presence of a smaller object and larger object respectively. the fod warning is asserted during the power transfer phase , indicating presenc e of a foreign object. with this warning on, the i dtp9030 stops power transfer, goes back to the ping phase , and stays there until the surface is cleared and the process starts over again.
idtp9030 product datasheet revision 1.0 .2 20 ? 2012 integrated device technology, inc. application s information f igure 15 . idtp9030 wpc qi compliance schematic (see idtp9030 valuation kit user manual for complete details) t h 1 1 0 k r 7 5 . 1 k j 1 i 2 c c o n n e c t o r 1 2 3 4 5 6 7 8 9 1 0 c 2 8 1 . 2 n f / 1 0 0 v r 2 3 2 . 7 k c 1 5 2 . 2 n c 1 4 2 2 u f / 2 5 v c 2 9 1 u c 7 2 2 u f / 2 5 v c 2 1 1 0 u / 2 5 v r 2 8 2 0 k r 2 4 1 0 k c 1 6 0 . 1 u / 5 0 v r 2 1 n p r 1 8 1 0 0 k r 2 9 1 0 k r 1 6 1 0 k r 3 1 1 . 5 k c 2 5 3 3 n f / 2 5 0 v r 3 0 2 0 k d 3 n p c 1 0 . 1 u f c 1 3 2 2 u f / 2 5 v c 6 0 . 1 u f u 1 i d t p 9 0 3 0 g p i o _ 6 1 n c 3 1 l x 2 6 s w 3 3 p g n d 3 2 g p i o _ 2 5 s w 3 4 s w 3 5 g p i o _ 4 3 g p i o _ 5 2 g p i o _ 3 4 s c l 8 s d a 9 r e s e t 1 2 p g n d 2 9 p g n d 3 0 v o s n s 2 7 x t a l _ c l k _ i n 1 0 g p i o _ 1 6 x t a l _ c l k _ o u t 1 1 g p i o _ 0 7 p g n d 2 8 n c 4 2 b u c k 5 v t _ s n s 2 5 n c 3 6 i n 3 7 i n 3 8 i n 3 9 i s n s 4 0 e n 1 3 r e f g n d 1 4 r e g _ i n 1 5 l d o 5 v 1 6 l d o 2 p 5 v 1 7 l d o 2 p 5 v _ i n 1 8 b u c k 5 v t 1 9 b s t 2 0 a g n d 2 1 d g n d 2 2 n c 2 3 b u c k 5 v t _ i n 2 4 n c 4 6 n c 4 5 n c 4 4 h p f 4 1 g n d 4 3 n c 4 7 n c 4 8 e p 4 9 r 8 5 . 1 k r 9 n p c 2 6 1 0 u f / 6 . 3 v c 2 2 0 . 1 u f d 1 r e d l 2 4 . 7 u h r 7 0 4 7 k c 5 1 0 0 n c 1 2 1 u u 2 2 4 l c 6 4 v s s 4 a 2 3 a 0 1 a 1 2 v c c 8 w p 7 s c l 6 s d a 5 r 1 7 1 0 k r 1 9 2 . 7 k c 2 0 . 1 u f c 1 9 4 . 7 n r 2 0 4 2 2 c 2 4 1 . 8 n f j 3 a c a d a p t e r 1 2 3 d 5 r 2 6 1 0 k c 8 1 u d 4 n p r 7 1 n p c 1 8 3 . 3 n r 2 7 4 7 k c 1 0 2 2 u f / 2 5 v c 2 3 3 3 n f / 2 5 0 v c 1 1 1 u c 2 7 2 2 n / 5 0 v b z 1 p s 1 2 4 0 p 0 2 c t 3 1 2 d 6 2 0 0 v d i o d e c 2 0 3 3 n f / 2 5 0 v r 2 2 4 7 k r 7 2 n p c 4 8 2 u f / 2 5 v o s c o n + r 1 0 n p r 6 9 n p c 9 1 u c 1 7 4 7 n f d 2 g r e e n l d o 2 p 5 _ o u t + 5 v v i n v i n v i n v i n w p l d o 2 p 5 _ o u t r e s e t l d o 5 _ o u t v i n + 5 v s c l s d a e n l d o 2 p 5 _ o u t l d o 5 _ o u t l d o 2 p 5 _ o u t l d o 2 p 5 _ o u t l d o 2 p 5 _ o u t v o l 1 , w p c t x - a 1 c o i l , 2 4 u h c 2 0 , c 2 3 , c 2 5 ( 2 x 4 7 n f / 2 5 0 v , c 0 g o r 3 x 3 3 n f / 2 5 0 v , c 0 g ) l e d a l e d b l e d c l e d d
idtp9030 product datasheet revision 1.0 .2 21 ? 2012 integrated device technology, inc. table 6 . idtp9030 wpc qi compliance bill of materials note 1: recommended capacitor temperature /dielectric and voltage ratings: 250v capacitors are recommended because 200vp - p voltage levels may appear on the resonance capacitors as stated in the wpc specification. c0g/npo - type capacitor values stay relatively constant with voltage while x7r and x5r ceramic cap acitor values de - rate from 40% to over 80%. the decision to use lower voltage 100v capacitors or other type temperature/dielectric capacitors is left to the end user. external components the idtp9030 requires a minimum number of external components for proper operation (see the bom in table 10). a complete design schematic compliant to the wpc qi standard is given in figure 19. it includes wpc qi led signaling, buzzer, thermistor circuit, and eeprom for loading idtp9030 firmware. i 2 c communication th e idtp9030 includes an i 2 c block which can support either i 2 c master or i 2 c slave operation. after power - on - reset (por) , the idtp 9030 will initially become i 2 c master for the purpose of uploading firmware from an external memory device , such as an eeprom . the i 2 c master mode on the idtp9030 does not support multi - master mode, and it is important for system designers to avoid any bus master conflict until the idtp 9030 has finished any firmware uploading and has released control of the bus as i 2 c master. a fter any firmware uploading from external memory is complete, and when the idtp 9030 begins normal operation, the idtp 9030 is normally configured by the f irmware to be exclusively in i 2 c slave mode. item # qty ref design description manufacturer part # pcb footprint 1 3 c2,c16,c22 cap cer 0.1uf 50v 10% x7r tdk c2012x7r1h104k/0.85 805 3 c20,c23,c25 option 1 cap cer 0.033uf 250v 5% np0/c0g 1 tdk c4532c0g2e333jt 1812 2 c20,c23 option 2 cap cer 0.047uf 250v 5% np0/c0g 1 tdk c4532c0g2e473jt 1812 3 5 c8,c9,c11,c12,c29 cap cer 1uf 25v 10% x7r taiyo yuden tmk107b7105ka-t 0603 4 4 c7, c10, c13, c14 cap cer 22uf 25v 10% x7r taiyo yuden tmk325b7226mm-tr 1210 5 1 c4 oscon 82uf 25v 20% 105degc panasonic 25svpf82m e7 5 1 c17 cap cer 0.047uf 16v 10% x7r murata grm188r71c473ka01d 0603 6 1 c21 cap cer 10uf 25v 10% x5r tdk c2012x5r1e106k 0805 7 1 c15 cap cer 2200pf 16v 10% x7r avx 0603yc222kat2a 603 8 1 c6 cap cer 0.1uf 50v 10% x7r murata grm188r71h104ka93d 0603 9 1 c26 cap cer 10uf 6.3v 10% x7r taiyo yuden jmk212b7106kg-t 805 10 1 c18 cap cer 3300pf 50v 5% np0/c0g 1 murata gcm1885c1h332ja16d 0603 11 1 c24 cap cer 1800pf 50v 5% np0/c0g 1 murata grm1885c1h182ja01d 0603 12 1 c27 cap cer 0.022uf 100v x7r 10% tdk c1608x7r2a223k 0603 12 1 c28 cap cer 1200pf 100v 5% np0/c0g 1 tdk c1608c0g2a122j 0603 13 1 c19 cap cer 4700pf 50v 5% np0/c0g 1 tdk cgj3e2c0g1h472j 0603 14 1 d6 diode switch 200v 250mw diodes inc bav21w-7-f sod123 15 1 d5 diode switch 75v 300ma micro comm co 1n4148w-tp sod123 16 1 l2 4.7uh 20% 580ma coilcraft xpl2010-472ml 2ml e&e y31-60014f tdk ttx-52-t2v toko x1387 18 1 r18 res 100k ohm 1/16w 1% yageo rc0402fr-07100kl 402 19 2 r28,r30 res 20.0k ohm 1/10w 1% panasonic erj-3ekf2002v 0603 20 1 r31 res 1.50k ohm 1/10w 1% panasonic erj-3ekf1501v 0603 20 1 r24 res 10.0k ohm 1/16w 1% yageo rc0402fr-0710kl 402 21 1 r29 res 10.0k ohm 1/10w 1% 0603 smd panasonic erj-3ekf1002v 603 22 1 r27 res 47k ohm 1/10w 5% panasonic erj-2gej473x 402 23 1 u1 ic eeprom 64kbit 400khz microchip 24aa64t-i/mny 8tdfn 24 1 u2 ic wireless power transmitter idt idtp9030 6x6x0.8-48tqfn wpc "qi" compliance components 1 1 d1 led smartled 630nm red osram l29k-g1j2-1-0-2-r18-z 0603_led 2 1 d2 led smartled green 570nm osram lg l29k-g2j1-24-z 0603_led 19 2 r7, r8 res 4.9k ohm 1/10w 5% panasonic erj-2rkf4991x 402 20 3 r16,r17,r24 res 10.0k ohm 1/16w 1% yageo rc0402fr-0710kl 402 21 1 r20 res 422 ohm 1/10w 1% panasonic erj-2rkf4220x 402 22 2 r19,r23 res 2.7k ohm 1/10w 5% panasonic erj-2gej272x 402 23 2 c1,c5 cap cer 0.1uf 50v 10% x7r murata grm188r71h104ka93d 0603 24 1 th1 thermistor ntc 10k ohm 1% rad tdk b57551g0103f000 through-hole 25 1 bz1 buzzer piezo 4khz pc mnt tdk ps1240p02ct3 12.2mmx3.5mm 53mmx53mm 2 17 1 l1 24uh transmitter coil wpc tx-a1
idtp9030 product datasheet revision 1.0 .2 22 ? 2012 integrated device technolo gy, inc. for maximum flexibility, the idtp9030 tries to communicate with the first address on the eeprom at 100khz. if no ack is received, communication is attempted at the other addresses at 300khz. eeprom the idtp9030 uses an external eeprom which contain s either standard or custom tx firmware. the external eeprom memo ry chip is pre - programmed with a standard start - up program that is automatically loaded when 19v power is applied. the idtp9030 uses i 2 c slave address 0x52 to access the eeprom. the idtp9030 slave address is 0x39. the eeprom can be reprogrammed to suit the needs of a specific application using the idtp9030 software to ol ( see the idtp9030 - qi demo board user manual for complete d etails) . the ic will look initially for an external eeprom and use the firmware built into the ic rom only if no custom firmware is found. a serial 8kbyte (8kx8 64kbits) external eeprom is sufficient. if the standard default/built - in firmware is not suitable for the application, custom rom options are possible. please contact idt sales for more information. idt wil l provide the appro priate image in the format best suited to the application. overview of standard gpio usage there are 7 gpios on the idtp9030 transmitter ic, of which five are available for use as follows: ? gpio0: red led _ a to indicate standby, fau lt conditions, and fod wa rnings; see table 7 . ? gpio2: temperat ure sensor input. contact idt for a spreadsheet facilitating selection and use of thermistors. ? gpio3: green led_b to indicate standby, power transfer, and power complete. table 7 lists how the red and green leds can be used to display information about the idtp9030s operating modes. the table a lso includes information about external resistors or internal pull up/down opt ions to select led modes. e ight of the ten led modes (those associated with advanced charging modes ) are currently designated as future modes. ? gpio4: ac or dc buzzer (o ptional) with resistor options for different buzzer configurations. ? gpio5 ledc and gpio6 ledd are for future development , and are currently not defined. led functions two gpios are use d to drive leds which indicate, through various on/off and illumination options, the state of charging and some possible fault conditions. a red l d indicates various fault and fod (foreign object detection) states. the green l d indicates power trans fer and charge complete state information. upon power up, the two leds together may optionally indicate the standby state and remain in this state until another of the defined operational states occurs as shown in figure 16 , one or two resistors configur e the defined led option combinations. the dc voltage set in this way is read one time during power - on to determine the led configuration. t o avoid interfering with the led operation, the useful dc voltage range must be limited to not greater than 1vdc. figure 16 . idtp9030 led resistor options . led pattern operational status definitions: blink slow: 1s on, 1s off, repeat . blink fast: 400ms on, 800ms off, 400ms on, 800ms off, repeat . the red fod warning led is synchronized with the buzzer (if implemented) such that a 400ms tone corresponds with the fod red led illumination and 800ms of silence corresponds with the led being off. during the 30s that the buzzer is off , the fod led must continue to blink. i d t p 9 0 3 0 t o a d c r a r b l d o 2 p 5 v _ o u t g p i o 3 r e s i s t o r t o s e t o p t i o n s l e d m o d e r e s i s t o r c o n f i g u r a t i o n
idtp9030 product datasheet revision 1.0 .2 23 ? 2012 integrated device technology, inc. table 7 C idtp9030 led re sistor optioning (not all options supported, shaded rows are for future development) . buzzer function an optional buzzer feature is supported on gpio4. the default configuration is an ac buzzer . t he signal is created by toggli ng gpio4 active - hig h/active - low at a 2khz frequency. buzzer action: power transfer indication the idtp9030 support s audible notification when the device operation successfully reaches the power transfer state. the duration of the power transfer indic ation sound is 400ms . the latency between reaching the power transfer state and sounding the buzzer does not exceed 500ms . additionally, the buzzer sound is concurrent within 250ms of any change to the led configuration indicating the start of p ower t ra nsfer. buzzer action: no power transfer due to foreign object detected (fod) when a major fod situation is detected such that , for safety reasons, power transfer is not initiated , or that power transfer is terminated, the buzzer is sounded in a repeating sequence: for 30 seconds: 400ms on , 800ms off , repeat next 30 seconds: off/silence (but no change to led on/off patterns) the pattern is r epeat ed while the error condition exists the buzzer is synchronized with the fod led such that the 400ms on tone corresponds with the red led illumination and 800ms off (no sound) corresponds with red led being off. decoupling /bulk capacitors as with any high - performanc e mixed - signal ic, the idtp9030 must be isolated from the system power supply noise to perform optimally . a decoupling capacitor of 0. 1f must be connected between each power supply and the pcb ground plane as close to these pins as possible. for optimum device performance, the decoupling capacitor must be mounted on the component side of the pcb. avoid the use of vias in the decouplin g circuit. additionally, medium value capacitors in the 22f range must be used at the vin input to minimize ripple current and voltage droop due to the large current requirements of the resonant half half - bridge driver . at least four 22f standby power transfer charge complete fault condition led1- green on blink slow on off off led2- red on off off on blink fast led1- green on blink slow on off off led2- red on off off on blink fast led1- green on blink slow on off off led2- red on off off on blink fast led1- green on blink slow on off off led2- red on off off on blink fast led1- green on blink slow on off off led2- red on off off on blink fast led1- green off blink slow on off off led2- red off off off on blink fast led1- green off blink slow on off off led2- red off off off on blink fast led1- green off blink slow on off off led2- red off off off on blink fast led1- green off blink slow on off off led2- red off off off on blink fast led1- green off blink slow on off off led2- red off off off on blink fast r1-r8 are created using combination of two 1% resistors. designates future option r8 pull down 10 1 r2 r3 standby leds off plus standby leds on 3 4 5 2 7 6 8 9 standby leds off plus standby leds off plus r5 pull up r6 r7 r4 r1 standby leds off plus standby leds off standby leds on plus standby leds on plus standby leds on plus standby leds on plus fod warning operational status led control option led select resistor value description led #/ color
idtp9030 product datasheet revision 1.0 .2 24 ? 2012 integrated device technolo gy, inc. capacitors mus t be used close to the in pins of the device. since the operating voltage is 18v to 20v, the value of the capacitors will decrease due to voltage derating characteristics. for example, a 22f x7r 25v capacitors value is actually 6f when operating at 20v . there must also be an 82f to 100f bulk capacitor connected at the node where the input voltage to the board is applied. a 25v oscon - type or aluminum electrolytic must be connected between the input supply and ground as shown in figure 20. oscon capaci tors have much lower esr than aluminum electrolytic capacitors and will reduce voltage ripple. adc considerations the gpio pins are connected internally to a successive approximation adc with a multiplexed input. the gpio pins that are connected to the ad c have limited input range , so attention must be paid to the maximum vin (2.5v) . 0.01f decoupling capacitors can be added to the gpio inputs to minimize noise. wpc tx - a1 coil the sw pin connects to a series - resonance circuit comprising a wpc type - a1 coil (~ 24 ? h) and a s eries resonant capacitor (~ 100nf) , as shown in figure s 8 and 9 . the inductor serves as the primary coil in a loosely - coupled transformer, the secondary of which is the inductor connected to the power receiver (idtp9020 or another receiver ). t h e tx - a1 power transmitter coil is mounted on a ferrite shield to reduce emi. the coil assembly can be mounted next to the idtp9030. either ground plane or grounded copper shielding can be added beneath the ferrite shield for added reduction in radiated electrical field emissions. the coil ground plane/shield must be connected to the idtp9030 ground plane by a single trace. resonance capacitors the resonance capacitors must be c0 g type dielectric and have a dc rating to 250v. the highest - efficiency combination is three 33nf in parallel to get the lowest esr. using a single 100nf o r two 47nf capacitors is also an option. the pa rt numbers are shown in table 6 . buck converter the input capacitors (c in ) must be connected directly between the power v in and power p gnd pins. the output capacitor (c out ) and power ground must be connected together to minimize any dc regulation errors caused by ground potential differences. the bootstrap pin requires a small capacitor; c o nnect a 47nf bootstrap capacitor rated above 25v between the bst pin and the lx pin. the output - sense connection to the f eedback pins must be separ ated from any power trace. connect the output - sense trace as close as possible to the load point to avoid additional load regulation errors. sensing through a high - current load trace will degrade dc load regulation. the power tra ces, including p gnd traces, the sw or out traces and the vin trace must be kept short, direct and wide to allow large current flow. the inductor connection to the sw or out pins must be as short as possible. use several via pads when routing between layers . ldo s input capacitor the input capacitors must be located as physically close as possible to the power pin ( ldo2p5v_in ) and power ground ( gnd). ceramic capacitors are recommended for their higher current operation and small profile. also, ceramic capacit ors are inherently more capable than are tantalum capacitors to withstand input current surges from low impedance sources such as batteries used in portable devices. typically, 10v - or 16v - rated capacitors are required. the recommended external components are shown in table 10. output capacitor for proper load voltage regulation and operational stability, a capacitor is req uired on the output of each ldo ( ldo2p5v and ldo5v) . the output capacitor must be placed as close to the device and power (pgnd) pins as possible. since the ldo s have been designed to function with very low esr capacitors, a ceramic capacitor is recommended for best performance. pcb layout considerations - for optimum device performance and lowest output phase noise, the following guid elines must be observed. please contac t idt for g erber files that contain the recommended board layout. - as for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step . if layout is not carefully done, the regulator could show
idtp9030 product datasheet revision 1.0 .2 25 ? 2012 integrated device technology, inc. instability as well as emi problems. therefore, use wide and short traces for high current paths. - the 0. 1f decoupling capacitors must be mounted on the component side of the board as close to the vdd pin as possible. do not use vias between decoupling capacitors and vdd pins. keep pcb trace s to each vdd pin and to ground via s as short as possible . - to optimize board layout , place all components on the same side of the board and limit the use of vias. route other signal traces away from the idtp9030 . for example, use keepouts for signal traces routing on inner and bottom layers underneath the device . - the nqg48 6 .0 mm x 6x0 mm x 75 mm 48l package has an inner thermal pad which requires blind assem bly. it is recommended that a more active flux solder paste be used such as alpha om - 350 solder paste from cookson electronics ( http://www.cooksonsemi.com ). please contact idt for g erber files that contain recomme nded solder stencil design. - the package center e xposed p ad (ep) must be reliably soldered directly to the pcb. the center land pad on the pcb (set 1:1 with ep) must also be tied to the board ground plane , primarily to maximize thermal performance in the a pplication. the g round connection is best achi e ved using a matrix of pth vias embedded in the pcb center land pad for the ntg48. the pth vias perform as thermal conduits to the ground plane (thermally, a heat spreader) as well as to the solder side of the board. there, these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side. recommendations for the via finished hole - size and array pi tc h are 0.3mm to 0.33mm and 1.3mm, respectively. - layout and pcb d esign have a significant influence on the power dissipation capabilities of power management ics. this is due to the fact that the surface mount packages used with these devices rely heavily on ther mally conductive traces or pads to transfer heat away from the package. appropriate pc layout techniques must then be used to remove the heat due to device power dissipation. the following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. pc board traces with large cros s sectional areas remove more heat. for optimum results, use large area pcb patterns with wide and heavy (2 oz.) copper traces, placed on the top layer of the pcb. 2. in cases where maximum heat dissipation is required, use double - sided copper planes connecte d with multiple vias. 3. thermal vias are needed to provide a thermal path to the inner and/or bottom layers of the pcb to remove the heat generated by device power dissipation. 4. where possible, increase the thermally conducting surface area(s) openly exposed to moving air, so that heat can be removed by convection (or forced air flow, if available). 5. do not use solder mask or place silkscreen on the heat - dissipating traces/pads, as they increase the net thermal resistance of the mounted ic package. power dissip ation/thermal requirements the idtp9030 is offered in a tqfn - 48l package . the m aximum pow er dissipation capability is 2 w , limited by the dies specified maximum operating junction temperature, tj, of 125 c . the junction temperature rise s with the device power dissipation based on the package thermal resistance. the package offers a typical thermal resistance, junction to ambient ( ? ja ), of 31 c/w when the pcb layout and surrounding devices are optimized as described in the pcb layout considerations section . the techniques as noted in the pcb layout section need to be followed when designing the printed circuit board layout, as well a s the placement of the idtp9030 ic package in proximity to other heat generating devices in a given application design. the am bient temperature around the power ic will also have an effect on the thermal limits of an application. the main factors influencing ja (in the order of decreasing influence) are pcb characteristics, die /package attach thermal pad size , and internal packa ge construction. board designers should keep in mind that the package thermal metric ja is impacted by the characteristics of the pcb itself up on which the tqfn is mounted. for example, in a still air environment, as is often the case, a significant amo unt of the heat that is generated (60 - 85%) sinks into the pcb. changing the design or configuration of the pcb changes impacts the overall thermal resistivity and, thus , the boards heat sinking efficiency .
idtp9030 product datasheet revision 1.0 .2 26 ? 2012 integrated device technolo gy, inc. implementation of integrated circuits in low - profile and fine - pitch surface - mount packages typically requires special attention to power dissipation. many system - dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat - generating co mponents, affect the power - dissipation limits of a given component. three basic approaches for enhancing thermal performance are listed below: 1. improving the power dissipation capability of the pcb design 2. improving the thermal coupling of the component to t he pcb 3. introducing airflow into the system first, the maximum power dissipation for a given situation must be calculated: p d(max) = (t j(max) - t a )/ ja where: p d(max) = maximum power dissipation (w) ja = package thermal resistance (c/w) t j(max) = maximum device junction temperature (c) t a = ambient temperature (c) the maximum recommended junction temperature ( t j(max) ) for the idtp9030 device is 1 5 0 c. t he thermal resistance of the 48 - pin nqg package (ngq48 ) is optimally ja =30 c/w. operation is specified to a maximum steady - state ambient temperature (t a ) of 85 c. therefore, the maximum recommended power dissipation is: p d(max) = ( 150c - 85c) / 30c/w 2 watt thermal overload protection the idtp9030 integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fa ult conditions. this circuitry will shut down or reset the dev ice if the die temperature exceeds 140 c. to allow the maximum load current on each regulator and resonant transmitter , and to prevent thermal overload, it is important to ensure that the heat generated by the idtp9030 is dissipated into the pcb. the packa ge exposed paddle must be soldered to the pcb, with multiple vias evenly distributed under the exposed paddle and exiting the bottom side of the pcb. this improves heat flow away from the package and minimizes package thermal gradients . special notes nqg tqfn - 48 package assembly note 1: unopened dry packaged parts have a one year shelf life. note 2: the hic indicator card for newly opened dry packaged parts should be checked . if there is any moisture content, the parts must be baked for minimum of 8 h ours at 125?c within 24 hours of the assembly reflow process.
idtp9030 product datasheet revision 1.0 .2 27 ? 2012 integrated device technology, inc. package outline draw ing figure 17 . idtp9030 package outline drawing (ntg48 tqfn - 48l 6.0 mm x 6.0 mm x 0.75 mm48l, 0.4mm pitch) p o d i n b o t t o m v i e w p o d i n s i d e v i e w c 0 . 3 5 d a p s i z e 4 . 5 x 4 . 5 1 1 2 3 6 2 4 4 8 1 3 3 7 2 5 d o n o t s c a l e d r a w i n g p k p a p p r o v a l s d r a w n c h e c k e d x x x x x x d e c i m a l . 0 3 0 . 1 . 0 5 1 2 / 0 4 / 0 9 s i z e c a n g u l a r d a t e 1 t i t l e u n l e s s s p e c i f i e d t o l e r a n c e s s h e e t o f 1 n t / n t g 4 8 p a c k a g e o u t l i n e 6 . 0 x 6 . 0 m m b o d y 0 . 4 m m p i t c h t q f n p s c - 4 2 9 4 d r a w i n g n o . 1 r e v 0 0 d e s c r i p t i o n i n i t i a l r e l e a s e r e v i s i o n s d c n 0 0 r e v a p p r o v e d d a t e 3 / 1 6 / 1 0 p h o n e : ( 4 0 8 ) 2 8 4 - 8 2 0 0 d i t f a x : ( 4 0 8 ) 2 8 4 - 3 5 7 2 w w w . i d t . c o m v a l l e y r o a d . s a n j o s e , 6 0 2 4 s i l v e r c r e e k t m c a 9 5 1 3 8
www.idt.com 6024 silver creek valley road san jose, california 95138 tel: 800 - 345 - 7015 disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the produ cts and/or specifications described herein at any time and at idts sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice . performance specifications and the opera ting parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in c ustomer products. the information contained herein is provided without representation or warranty of any kin d, whether express or implied, including, but not limited to, the suitability of idts products for any particular purpose, a n implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presente d only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idts products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt product can be r easonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an expre ss, written agreement by idt. integrated device technology, idt and the idt logo are registere d trademarks of idt. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. ? copyright 2012 . all rights reserved. vpaxxxx preliminary product data ordering guide table 8 . orderi ng summary part number marking package ambient temp. range shipping carrier quantity p9030 - 0 ntg i p9030ntg ntg48 - tqfn - 48 6x6x0.75mm - 40c to +85c tape or canister 25 p9030 - 0 ntg i 8 p9030ntg ntg48 - tqfn - 48 6x6x0.75mm - 40c to +85c tape and reel 2,500

▲Up To Search▲

Price & Availability of P9030-0NTGI8

	To Download P9030-0NTGI8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .